1. Field of the Invention
The present invention relates to an interconnects-forming method and an interconnects-forming apparatus, and more particularly to an interconnects-forming method and an interconnects-forming apparatus for forming interconnects by filling an interconnect material (metal) into fine recesses for interconnects formed in a surface of a substrate, such as a semiconductor wafer.
2. Description of the Related Art
In recent years, instead of using aluminum or aluminum alloys as a material for forming interconnect circuits on a substrate such as a semiconductor wafer, there is an eminent movement towards using copper (Cu) which has a low electric resistivity and high electromigration resistance. Copper interconnects are generally formed by filling copper into fine interconnect recesses formed in a surface of a substrate. Various techniques for forming such copper interconnects are known, including CVD, sputtering, and plating. According to any such technique, a copper film is formed in a substantially entire surface of a substrate, followed by removal of unnecessary copper by chemical-mechanical polishing (CMP).
In the case of interconnects formed by such a process, embedded interconnects have exposed surfaces after performing a flattening processing. When an additional embedded interconnect structure is formed on such interconnects-exposed surface of a substrate, the following problems maybe encountered. For example, during formation of a new SiO2 or a low-k material in a sequence process for forming an interlevel insulating film, exposed surfaces of pre-formed interconnects are likely to be oxidized. Further, upon etching of the SiO2 or the low-k material for formation of via holes, the pre-formed interconnects exposed on the bottoms of the via holes can be contaminated with an etchant, a peeled resist, and the like.
In order to avoid such problems, it has been conventional to form a protective film of SiN or the like not only on a circuit-formed region of a substrate where surfaces of interconnects are exposed, but also on an entire surface of the substrate, thereby preventing contamination of these interconnects with an etchant, and the like.
However, when a protective film of SiN or the like, which generally has a low bonding power or adhesion to an interconnect material such as copper, is formed on an entire surface of a substrate, electrons are likely to move between interconnects and the protective film caused by electromigration. Furthermore, in a semiconductor device having an embedded interconnect structure, as a protective film generally has high dielectric constant k than a dielectric constant k of the conventional interlevel insulating film, the dielectric constant of the interlevel insulating film increases, thus inducing delayed interconnections even when a low-resistivity material such as copper or silver is employed for interconnects, whereby the performance of the semiconductor device may be impaired.
In view of this, it has been proposed to selectively cover surfaces of exposed interconnects with a protective film of Co (Cobalt), a Co alloy, Ni (Nickel) or a Ni alloy, exhibiting a good adhesion to an interconnect material such as copper or silver and having a low resistivity (ρ), for example, an alloy film which is obtained by electroless plating.
FIGS. 1A through 1D illustrate, in sequence of process steps, an example of forming such a semiconductor device having copper interconnects. As shown in FIG. 1A, an insulating film 2, such as an oxide film of SiO2 or a film of low-k material, is deposited on a conductive layer 1a on a semiconductor base 1 having formed semiconductor devices. Contact holes 3 and interconnect trenches 4 for interconnect recesses are formed in the insulating film 2 by the lithography/etching technique. Thereafter, a barrier layer 5 of TaN or the like is formed on the insulating film 2, and a seed layer 6 as an electric supply layer for electroplating is formed on the barrier layer 5 by sputtering or the like.
Then, as shown in FIG. 1B, copper plating is performed onto the surface of the substrate W to fill the contact holes 3 and the interconnect trenches 4 of the substrate W with copper and, at the same time, deposit a copper film 7 on the insulating film 2. Thereafter, the barrier layer 5, the seed layer 6 and the copper film 7 on the insulating film 2 are removed by chemical-mechanical polishing (CMP) so as to make the surface of the copper film 7 filled in the contact holes 3 and the interconnect trenches 4, and the surface of the insulating film 2 lie substantially on the same plane. Interconnects (copper interconnects) 8 composed of the seed layer 6 and the copper film 7, as shown in FIG. 1C, is thus formed in the insulating film 2.
Then, as shown in FIG. 1D, electroless plating is performed onto the surface of the substrate W to form a protective film 9 of a Co alloy, a Ni alloy or the like on the surfaces of interconnects 8 selectively, thereby covering and protecting the surfaces of interconnects 8 with the protective film 9.
However, according to the conventional process for selectively covering and protecting the exposed surfaces of interconnects with a protective film, the protective film protrudes from the surface of an insulating film whereby the surface loses its flatness. When second-level interconnects are formed on first-level interconnects in the production of a multi-level interconnect structure, irregularities reflecting the shape of a protective film are produced on the surface of an interlevel insulating film deposited on the surface of the first-level interconnects, and the irregularities of the surface of the interlevel insulating film affect the processing accuracy in later etching, light exposure or the like processing for the formation of interconnect recesses. Further, unless the film thickness of the selectively formed protective film is controlled optimally, there may occur a case where adjacent protective films are too close to each other, and trouble, such as dissolution of the protective film or a barrier layer, can occur. This may result in generation of a leakage current that can lower the electrical properties of interconnects.